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1 general description the DS1339A serial real-time clock (rtc) is a low- power clock/date device with two programmable time- of-day alarms and a programmable square-wave output. address and data are transferred serially through an i 2 c bus. the clock/date provides seconds, minutes, hours, day, date, month, and year information. the date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. the clock operates in either the 24-hour or 12-hour format with am/pm indicator. the DS1339A has a built- in power-sense circuit that detects power failures and automatically switches to the backup supply, maintaining time, date, and alarm operation. applications handhelds (gps, pos terminals) consumer electronics (set-top box, digital recording, network appliance) office equipment (fax/printers, copier) medical (glucometer, medicine dispenser) telecommunications (routers, switches, servers) other (utility meter, vending machine, thermostat, modem) features s drop-in replacement for ds1339 s real-time clock (rtc) counts seconds, minutes, hours, day, date, month, and year with leap-year compensation up to 2200 s i 2 c serial interface s two time-of-day alarms s programmable square-wave output s oscillator stop flag s automatic power-fail detect and switch circuitry s trickle-charge capability functional diagram 19-6425; rev 0; 8/12 ordering information appears at end of data sheet. for related parts and recommended products to use with this part, refer to www.maxim-ic.com/DS1339A.related . DS1339A n n /4 /4096 control logic oscillator and divider alarms, trickle charger, and control registers clock and calendar registers user buffer (7 bytes) /2 1hz sqw/intb x1 x2 4.096khz 8.192khz 32.768khz mux/ buffer serial bus interface and address register power control scl sda v cc v backup DS1339A low-current, i 2 c, serial real-time clock for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com.
2 DS1339A low-current, i 2 c, serial real-time clock voltage range on any pin relative to ground .... -0.3v to +6.0v operating temperature range (noncondensing) .... -40 n c to +85 n c storage temperature range ............................ -55 n c to +125 n c lead temperature (soldering, 10 seconds) ................... +300 n c soldering temperature (reflow) ...................................... +260 n c sop junction-to-ambient thermal resistance ( b ja ) ..... 206.3 n c/w junction-to-case thermal resistance ( b jc ) ............... 42 n c/w absolute maximum ratings note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional opera - tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics (note 1) recommended operating conditions (t a = -40 n c to +85 n c, unless otherwise noted.) (note 2) dc electrical characteristics ( v cc = min to max , v backup = min to max, t a = -40 n c to +85 n c.) (note 2) parameter symbol conditions min typ max units supply voltage v cc 1.71 3.3 5.5 v backup supply voltage v backup 1.3 3.0 3.7 v v backmin 1.15 1.3 logic 1 v ih 0.7 x v cc 5.5 v logic 0 v il -0.3 0.3 x v cc v power-fail voltage v pf 1.51 1.61 1.71 v parameter symbol conditions min typ max units input leakage i li (note 3) -0.1 0.1 f a i/o leakage i lo (note 4) -0.1 0.1 f a logic 0 out (sda or sqw/ int ) v ol = 0.4v, v cc r v ccmin i ol (note 4) 3 ma logic 0 out (sqw/ int ) v ol = 0.2v, v cc = 0v, v bat r v batmin i ol (note 4) 250 f a v cc active current i cca (note 5) 450 f a v cc standby current i ccs (note 6) 200 f a trickle-charger resistor register 10h = a5h, v cc = typ, v backup = 0v r1 (note 7) 200 i
3 DS1339A low-current, i 2 c, serial real-time clock dc electrical characteristics ( continued ) ( v cc = min to max , v backup = min to max, t a = -40 n c to +85 n c, unless otherwise noted.) (note 2) dc electrical characteristics ( v cc = 0v , v backup = min to max, t a = -40 n c to +85 n c, unless otherwise noted.) (note 2) ac electrical characteristics (v cc = min to max, t a = -40 n c to +85 n c, unless otherwise noted.) (note 2, figure 1 ) parameter symbol conditions min typ max units trickle-charger resistor register 10h = a6h, v cc = typ, v backup = 0v r2 2000 i trickle-charger resistor register 10h = a7h, v cc = typ, v backup = 0v r3 4000 i v backup leakage current i bklkg -100 25 200 na parameter symbol conditions min typ max units v backup current eosc = 0, sqw off i bkosc (note 8) 300 600 na v backup current eosc = 0, sqw on i bksqw (note 8) 500 1100 na v backup current eosc = 1 i bkdr 10 200 na parameter symbol conditions min typ max units scl clock frequency f scl 0.03 400 khz bus free time between a stop and start condition t buf 1.3 f s hold time (repeated) start condition t hd:sta (note 9) 0.6 f s low period of scl clock t low 1.3 f s high period of scl clock t high 0.6 f s setup time for a repeated start condition t su:sta 0.6 f s data hold time t hd:dat (notes 10, 11) 0 0.9 f s data setup time t su:dat (note 12) 100 ns rise time of both sda and scl signals t r (note 13) 20 + 0.1c b 300 ns fall time of both sda and scl signals t f (note 13) 20 + 0.1c b 300 ns setup time for stop condition t su:sto 0.6 f s
4 DS1339A low-current, i 2 c, serial real-time clock warning: under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery-backup mode. note 2: limits are 100% production tested at t a = +25 n c and t a = +85 n c. limits over the operating temperature range and rel - evant supply voltage range are guaranteed by design and characterization. typical values are not guaranteed. note 3: scl only. note 4: sda and sqw/int. note 5: i cca scl at f scl max, v il = 0.0v, v ih = v cc , trickle charger disabled. note 6: specified with the i 2 c bus inactive, v il = 0.0v, v ih = v cc , trickle charger disabled. note 7: v cc must be less than 3.63v if the 200 i resistor is selected. note 8: using recommended crystal on x1 and x2. note 9: after this period, the first clock pulse is generated. note 10: a device must internally provide a hold time of at least 300ns for the sda signal (referred to the v ihmin of the scl signal) to bridge the undefined region of the falling edge of scl. note 11: the maximum t hd:dat need only be met if the device does not stretch the low period (t low ) of the scl signal. note 12: a fast-mode device can be used in a standard-mode system, but the requirement t su:dat r to 250ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r(max) + t su:dat = 1000 + 250 = 1250ns before the scl line is released. note 13: c b total capacitance of one bus line in pf. note 14: guaranteed by design; not production tested. note 15: the parameter t osf is the period of time the oscillator must be stopped for the osf flag to be set. note 16: the DS1339A can detect any single scl clock held low longer than t timeoutmin . the devices i 2 c interface is in reset state and can receive a new start condition when scl is held low for at least t timeoutmax . once the device detects this condition, the sda output is released. the oscillator must be running for this function to work. note 17: this delay applies only if the oscillator is running. if the oscillator is disabled or stopped, no power-up delay occurs. ac electrical characteristics ( continued ) (v cc = min to max, t a = -40 n c to +85 n c, unless otherwise noted.) (note 2, figure 1 ) power-up/down characteristics (t a = -40 n c to +85 n c, unless otherwise noted.) (note 2, figure 2 ) parameter symbol conditions min typ max units capacitive load for each bus line c b (note 13) 400 pf i/o capacitance (sda, scl) c i/o (note 14) 10 pf oscillator stop flag (osf) delay t osf (note 15) 100 ms timeout interval t timeout (note 16) 25 35 ms parameter symbol conditions min typ max units recovery at power-up t rec (note 17) 1 2 ms v cc slew rate; v pf to 0v t vccf 1/50 v/ f s v cc slew rate; 0v to v pf t vccr 1/1 v/ f s
5 DS1339A low-current, i 2 c, serial real-time clock figure 1. i 2 c timing figure 2. power-up/down timing scl note: timing is referenced to v il(max) and v ih(min) . sda stop start repeated start t buf t hd:sta t hd:dat t su:dat t su:sto t hd:sta t sp t su:sta t high t r t f t low recognized don?t care recognized scl valid valid sda high impedance t rec t vccr t vccf v pf v cc
6 typical operating characteristics (v cc = 3.3v, t a = +25 n c, unless otherwise noted.) trickle charger resistors vs. power supply voltage DS1339A toc07 power supply voltage (v) resistance () 4.7 3.7 2.7 500 1000 1500 2000 2500 3000 3500 4000 0 1.7 5.7 t a = +25c 4k selected 2k selected 200 selected int/sqw output current vs. output voltage DS1339A toc06 output current (ma) output voltage (v) 1.5 1.0 0.5 0.1 0.2 0.3 0.4 0 0 2.0 v backup = 1.3v, v cc = 0v, t a = +25c int/sqw output current vs. output voltage DS1339A toc05 output current (ma) output voltage (v) 8 6 2 4 0.1 0.2 0.3 0.4 0.6 0.5 0.7 0.8 0 01 0 v cc = 1.71v, t a = +25c backup supply current vs. backup voltage DS1339A toc04 backup voltage (v) backup current (na) 3.3 2.3 300 350 400 450 500 550 600 650 250 1.3 4.3 v cc = 0v, sqw on, i out = 0ma t a = +85c t a = +25c t a = -40c backup supply current vs. backup voltage DS1339A toc03 backup voltage (v) backup current (na) 3.3 2.3 150 200 250 300 350 400 450 500 100 1.3 4.3 v cc = 0v, sqw off t a = +85c t a = +25c t a = -40c power supply current vs. scl frequency DS1339A toc02 supply voltage (v) supply current (ma) 4.7 3.7 2.7 100 150 200 250 300 350 400 450 50 1.7 5.7 v cc = sda, v backup = 3v f scl = 400khz f scl = 100khz f scl = 1khz power supply current vs. power supply voltage DS1339A toc01 supply voltage (v) supply current (a) 4.7 3.7 2.7 60 80 100 120 140 160 180 40 1.7 5.7 v cc = scl = sda, v backup = 3v t a = +85c t a = +25c t a = -40c DS1339A low-current, i 2 c, serial real-time clock
7 DS1339A low-current, i 2 c, serial real-time clock pin configuration pin description pin name function 1 x1 connections for standard 32.768khz quartz crystal. the internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (c l ) of 6pf. for more information about crystal selection and crystal layout considerations, see the applications information section and refer to application note 58: crystal considerations with dallas real-time clocks . 2 x2 3 v backup secondary power supply. supply voltage must be held between 1.3v and 3.7v for proper operation. this pin can be connected to a primary cell, such as a lithium coin cell. additionally, this pin can be connected to a rechargeable cell or a super cap when used in conjunction with the trickle-charge feature. diodes should not be placed in series between the backup source and the v backup input, or improper operation will result. if a backup supply is not required, v backup must be grounded. ul recognized to ensure against reverse charging current when used with a primary lithium cell. for more information, visit www.maxim-ic.com/qa/info/ul . 4 gnd ground 5 sda serial data input/output. sda is the input/output pin for the i 2 c serial interface. the sda pin is an open- drain output and requires an external pullup resistor. the pull up voltage may be up to 5.5v regardless of the voltage on v cc . 6 scl serial clock input. scl is used to synchronize data movement on the i 2 c serial interface. the pull up voltage may be up to 5.5v regardless of the voltage on v cc . 7 sqw/ int square-wave/interrupt output. programmable square-wave or interrupt output signal. the sqw/ int pin is an open-drain output and requires an external pullup resistor. the pull up voltage may be up to 5.5v regardless of the voltage on v cc . if not used, this pin may be left unconnected. 8 v cc primary power supply. when voltage is applied within normal limits, the device is fully accessible and data can be written and read. when a backup supply is connected and v cc is below v pf , reads and writes are inhibited. the timekeeping and alarm functions operate when the device is powered by v cc or v backup . sop 27 sqw/int x2 18 v cc + x1 scl v backup 36 sda gnd top view 45 DS1339A
8 DS1339A low-current, i 2 c, serial real-time clock detailed description the DS1339A serial real-time clock (rtc) is a low- power clock/date device with two programmable time- of-day alarms and a programmable square-wave output. address and data are transferred serially through an i 2 c bus. the clock/date provides seconds, minutes, hours, day, date, month, and year information. the date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. the clock operates in either the 24-hour or 12-hour format with am/pm indicator. the DS1339A has a built- in power-sense circuit that detects power failures and automatically switches to the backup supply, maintaining time, date, and alarm operation. operation the DS1339A operates as a slave device on the serial bus. access is obtained by implementing a start condition and providing a device identification code followed by data. subsequent registers can be accessed sequentially until a stop condition is executed. the device is fully accessible and data can be written and read when v cc is greater than v pf . however, when v cc falls below v pf , the internal clock registers are blocked from any access. if v pf is less than v backup , the device power is switched from v cc to v backup when v cc drops below v pf . if v pf is greater than v backup , the device power is switched from v cc to v backup when v cc drops below v backup . the registers are maintained from the v backup source until v cc is returned to nominal levels. the functional diagram shows the main elements of the serial real-time clock. power control the power-control function is provided by a precise, temperature-compensated voltage reference and a comparator circuit that monitors the v cc level. the device is fully accessible and data can be written and read when v cc is greater than v pf . however, when v cc falls below v pf , the internal clock registers are blocked from any access. if v pf is less than v backup , the device power is switched from v cc to v backup when v cc drops below v pf . if v pf is greater than v backup , the device power is switched from v cc to v backup when v cc drops below v backup . the registers are maintained from the v backup source until v cc is returned to nominal levels ( table 1 ). after v cc returns above v pf , read and write access is allowed after t rec ( figure 2 ). on the first application of power to the device the time and date registers are reset to 01/01/00 01 00:00:00 (dd/mm/yy dow hh:mm:ss). oscillator circuit the DS1339A uses an external 32.768khz crystal. the oscillator circuit does not require any external resistors or capacitors to operate. table 2 specifies several crystal parameters for the external crystal. the functional diagram shows a basic schematic of the oscillator circuit. the startup time is usually less than 1 second when using a crystal with the specified characteristics. table 1. power control table 2. crystal specifications* * the crystal, traces, and crystal input pins should be isolated from rf generating signals. refer to application note 58: crystal considerations for dallas real-time clocks for addi - tional specifications. supply condition read/ write access powered by v cc < v pf , v cc < v backup no v backup v cc < v pf , v cc > v backup no v cc v cc > v pf , v cc < v backup yes v cc v cc > v pf , v cc > v backup yes v cc parameter symbol min typ max units nominal frequency f o 32.768 khz series resistance esr 60 k i load capacitance c l 6 pf
9 DS1339A low-current, i 2 c, serial real-time clock clock accuracy the accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. additional error is added by crystal frequency drift caused by temperature shifts. external circuit noise coupled into the oscillator circuit may result in the clock running fast. figure 6 shows a typical pc board layout for isolating the crystal and oscillator from noise. refer to application note 58: crystal considerations with dallas real-time clocks for detailed information rtc address map table 3 shows the address map for the DS1339A registers. during a multibyte access, when the address pointer reaches the end of the register space (10h), it wraps around to location 00h. on an i 2 c start or address pointer incrementing to location 00h, the current time is transferred to a second set of registers. the time information is read from these secondary registers, while the clock may continue to run. this eliminates the need to re-read the registers in case of an update of the main registers during a read. time and date operation the time and date information is obtained by reading the appropriate register bytes. table 3 shows the rtc registers. the time and date are set or initialized by writing the appropriate register bytes. the contents of the time and date registers are in the bcd format. the DS1339A can be run in either 12-hour or 24-hour mode. bit 6 of the hours register is defined as the 12- or 24-hour mode-select bit. when high, the 12-hour mode is selected. in the 12-hour mode, bit 5 is the am /pm bit with logic high being pm. in the 24-hour mode, bit 5 is the 20-hour bit (20 to 23 hours). all hours values, including the alarms, must be re-entered whenever the 12/ 24 -hour mode bit is changed. the century bit (bit 7 of the month register) is toggled when the year register overflows from 99 to 00. if the century bit is logic 0, the year will be designated as a leap year and february will contain 29 days. if the century bit is logic 1, the year will not be designated as a leap year and february will contain 28 days. the day-of-week register increments at midnight. values that correspond to the day of week are user-defined, but must be sequential (i.e., if 1 equals sunday, then 2 equals monday and so on). illogical time and date entries result in undefined operation. when reading or writing the time and date registers, secondary (user) buffers are used to prevent errors when the internal registers update. when reading the time and date registers, the user buffers are synchronized to the internal registers on a start or when the address pointer rolls over to 00h. the countdown chain is reset whenever the seconds register is written. write transfers occurs on the acknowledge pulse from the device. to avoid rollover issues, once the countdown chain is reset, the remaining time and date registers must be written within one second. if enabled, the 1hz square-wave output transitions high 500ms after the seconds data transfer, provided the oscillator is already running.
10 DS1339A low-current, i 2 c, serial real-time clock table 3. timekeeping register map 0 - reads as logic 0. note: unless otherwise specified, the state of the registers are not defined when power is first applied or when v cc and v backup fall below the v backup(min) . address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 function range 00h 0 10 seconds seconds seconds 00-59 01h 0 10 minutes minutes minutes 00-59 02h 0 12/ 24 am /pm 10 hour hours hours 01-12 +am/pm 00-23 20 hour 03h 0 0 0 0 0 day day 01-07 04h 0 0 10 date date 01-31 05h century 0 0 10 month month month 01-12 +century 06h 10 year year year 00-99 07h a1m1 10 seconds seconds alarm 1 seconds 00-59 08h a1m2 10 minutes minutes alarm 1 minutes 00-59 09h a1m3 12/ 24 am /pm 10 hour hours alarm 1 hours 01-12 +am/pm 00-23 20 hour 0ah a1m4 dy/ dt 10 date day, date alarm 1 day, alarm 1 date 01-07, 01-31 0bh a2m2 10 minutes minutes alarm 2 minutes 00-59 0ch a2m3 12/ 24 am /pm 10 hour hours alarm 2 hours 01-12 +am/pm 00-23 20 hour 0dh a2m4 dy/ dt 10 date day, date alarm 2 day, alarm 2 date 01-07, 01-31 0eh eosc 0 bbsqi rs2 rs1 intcn a2ie a1ie control - 0fh osf 0 0 0 0 0 a2f a1f status - 10h tcs3 tcs2 tcs1 tcs0 ds1 ds0 rout1 rout0 trickle charger -
11 DS1339A low-current, i 2 c, serial real-time clock alarms the DS1339A contains two time of day/date alarms. alarm 1 can be set by writing to registers 07h to 0ah. alarm 2 can be set by writing to registers 0bh to 0dh. the alarms can be programmed (by the alarm enable and intcn bits of the control register) to activate the sqw/ int output on an alarm match condition. bit 7 of each of the time of day/date alarm registers are mask bits ( table 4 ). when all the mask bits for each alarm are logic 0, an alarm only occurs when the values in the timekeeping registers 00h to 06h match the values stored in the time of day/date alarm registers. the alarms can also be programmed to repeat every second, minute, hour, day, or date. table 4 shows the possible settings. configurations not listed in the table result in illogical operation. the dy/ dt bits (bit 6 of the alarm day/date registers) control whether the alarm value stored in bits 0 to 5 of that register reflects the day of the week or the date of the month. if dy/ dt is written to a logic 0, the alarm is the result of a match with date of the month. if dy/ dt is written to a logic 1, the alarm is the result of a match with day of the week. the device checks for an alarm match once per second. when the rtc register values match alarm register settings, the corresponding alarm flag a1f or a2f bit is set to logic 1. if the corresponding alarm interrupt enable a1ie or a2ie is also set to logic 1 and the intcn bit is set to logic 1, the alarm condition activates the sqw/ int signal. if the bbsqi bit is set to 1, the int output activates while the part is being powered by v backup . the alarm output remains active until the alarm flag is cleared by the user. table 4. alarm mask bits dy/ dt alarm1 register mask bits (bit 7) alarm rate a1m4 a1m3 a1m2 a1m1 x 1 1 1 1 alarm once per second x 1 1 1 0 alarm when seconds match x 1 1 0 0 alarm when minutes and seconds match x 1 0 0 0 alarm when hours, minutes, and seconds match 0 0 0 0 0 alarm when date, hours, minutes, and seconds match 1 0 0 0 0 alarm when day, hours, minutes, and seconds match dy/ dt alarm2 register mask bits (bit 7) alarm rate a2m4 a2m3 a2m2 x 1 1 1 alarm once per minute (00 sec. of every minute) x 1 1 0 alarm when minutes match x 1 0 0 alarm when hours and minutes match 0 0 0 0 alarm when date, hours, and minutes match 1 0 0 0 alarm when day, hours, and minutes match
12 DS1339A low-current, i 2 c, serial real-time clock control register (0eh) the control register controls the operation of the sqw/ int pin and provides oscillator status. bit 7: enable oscillator ( eosc ). when the eosc bit is 0, the oscillator is enabled. when this bit is a 1, the oscillator is disabled. this bit is cleared (0) when power is first applied. bit 5: battery-backed square-wave interrupt (bbsqi). when set to logic 1, this bit enables the sqw/ int output functionality while the part is powered by v backup . when set to logic 0, this bit disables the sqw/ int output while the part is powered by v backup . bits 4 and 3: rate select (rs2 and rs1). these bits control the frequency of the sqw/ int output when the square- wave has been enabled (intcn=0). table 5 lists the square-wave frequencies that can be selected with the rs bits. bit 2: interrupt control (intcn). this bit controls the relationship between the two alarms and the interrupt output pin. when the intcn bit is set to logic 1, a match between the timekeeping registers and the alarm 1 or alarm 2 registers activate the sqw/ int pin (provided that the alarm is enabled). when the intcn bit is set to logic 0, a square wave is output on the sqw/ int pin. this bit is set to logic 0 when power is first applied. bit 1: alarm 2 interrupt enable (a2ie). when set to a logic 1, this bit permits the alarm 2 flag (a2f) bit in the status register to assert sqw/ int (when intcn = 1). when the a2ie bit is set to logic 0 or intcn is set to logic 0, the a2f bit does not initiate an interrupt signal. the a2ie bit is disabled (logic 0) when power is first applied. bit 0: alarm 1 interrupt enable (a1ie). when set to logic 1, this bit permits the alarm 1 flag (a1f) bit in the status register to assert sqw/ int (when intcn = 1). when the a1ie bit is set to logic 0 or intcn is set to logic 0, the a1f bit does not initiate an interrupt signal. the a1ie bit is disabled (logic 0) when power is first applied. table 5. sqw/ int output intcn rs2 rs1 sqw/ int output a2ie a1ie 0 0 0 1hz x x 0 0 1 4.096khz x x 0 1 0 8.192khz x x 0 1 1 32.768khz x x 1 x x a1f 0 1 1 x x a2f 1 0 1 x x a2f + a1f 1 1 bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name eosc 0 bbsqi rs2 rs1 intcn a2ie a1ie por 0 0 0 1 1 0 0 0
13 DS1339A low-current, i 2 c, serial real-time clock status register (0fh) the control register controls the operation of the sqw/ int pin and provides oscillator status. bit 7: oscillator stop flag (osf). a logic 1 in this bit indicates that the oscillator has stopped or was stopped for some time period and can be used to judge the validity of the clock and calendar data. this bit is edge triggered, and is set to logic 1 when the internal circuitry senses the oscillator has transitioned from a normal run state to a stopped condition. the following are examples of conditions that may cause the osf bit to be set: the first time power is applied. the voltage present on v cc and v bat are insufficient to support oscillation. the eosc bit is set to 1, disabling the oscillator. external influences on the crystal (i.e., noise, leakage, etc.). this bit remains at logic 1 until written to logic 0. this bit can only be written to logic 0. attempting to write osf to logic 1 leaves the value unchanged. bit 1: alarm 2 flag (a2f). a logic 1 in the alarm 2 flag bit indicates that the time matched the alarm 2 registers. if the a2ie bit is a logic 1 and the intcn bit is set to a logic 1, the sqw/ int pin is also asserted. a2f is cleared when written to logic 0. this bit can only be written to logic 0. attempting to write to logic 1 leaves the value unchanged. bit 0: alarm 1 flag (a1f). a logic 1 in the alarm 1 flag bit indicates that the time matched the alarm 1 registers. if the a1ie bit is a logic 1 and the intcn bit is set to a logic 1, the sqw/ int pin is also asserted. a1f is cleared when written to logic 0. this bit can only be written to logic 0. attempting to write to logic 1 leaves the value unchanged. bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name osf 0 0 0 0 0 a2f a1f por 1 0 0 0 0 0 0 0
14 DS1339A low-current, i 2 c, serial real-time clock trickle charger (10h) the simplified schematic in figure 3 shows the basic components of the trickle charger. the trickle-charge select bits (tcs[3:0]) control the selection of the trickle charger. to prevent accidental enabling, only a pattern on 1010 enables the trickle charger. all other patterns disable the trickle charger. the trickle charger is disabled when power is first applied. the diode-select (ds[1:0]) bits select whether or not a diode is connected between v cc and v backup . the rout[1:0] bits select the value of the resistor connected between v cc and v backup . table 6 shows the register settings. figure 3. trickle charger warning: the rout value of 200 i must not be selected whenever v cc is greater than 3.63v. the user determines diode and resistor selection according to the maximum current desired for battery or super cap charging. the maximum charging current can be calculated as illustrated in the following example. assume that a 3.3v system power supply is applied to v cc and a super cap is connected to v backup . also assume that the trickle charger has been enabled with a diode and resistor r2 between v cc and v backup . the maximum current i max would therefore be calculated as follows: i max = (3.3v - diode drop) / r2 (3.3v - 0.7v) / 2k i 1.3ma as the super cap or battery charges, the voltage drop between v cc and v backup decreases and therefore the charge current decreases. table 6. trickle charger register (10h) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 function tcs3 tcs2 tcs1 tcs0 ds1 ds0 rout1 rout0 x x x x 0 0 x x disabled x x x x 1 1 x x disabled x x x x x x 0 0 disabled 1 0 1 0 0 1 0 1 no diode, 200 i resistor 1 0 1 0 1 0 0 1 one diode, 200 i resistor 1 0 1 0 0 1 1 0 no diode, 2k i resistor 1 0 1 0 1 0 1 0 one diode, 2k i resistor 1 0 1 0 0 1 1 1 no diode, 4k i resistor 1 0 1 0 1 0 1 1 one diode, 4k i resistor 0 0 0 0 0 0 0 0 initial power-up values r1 200 r2 2k r3 4k v cc v backup bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tcs3 tcs2 tcs1 tcs0 ds1 ds0 rout1 rout0 trickle- charge register 1 0f 16 select note: only 1010 code enables charger 1 of 2 select 1 of 3 select tcs[3:0] = trickle-charge select ds[1:0] = diode select rout[1:0] = resistor select
15 DS1339A low-current, i 2 c, serial real-time clock i 2 c serial port operation i 2 c slave address the DS1339As slave address byte is d0h. the first byte sent to the device includes the device identifier and the r/ w bit ( figure 4 ). the device address sent by the i 2 c master must match the address assigned to the device. i 2 c definitions the following terminology is commonly used to describe i 2 c data transfers. master device: the master device controls the slave devices on the bus. the master device generates scl clock pulses and start and stop conditions. slave devices: slave devices send and receive data at the masters request. bus idle or not busy: time between stop and start conditions when both sda and scl are inactive and in their logic-high states. when the bus is idle it often initiates a low-power mode for slave devices. start condition: a start condition is generated by the master to initiate a new data transfer with a slave. transitioning sda from high to low while scl remains high generates a start condition. see figure 1 for applicable timing. stop condition: a stop condition is generated by the master to end a data transfer with a slave. transitioning sda from low to high while scl remains high generates a stop condition. see figure 1 for applicable timing. repeated start condition: the master can use a repeated start condition at the end of one data transfer to indicate that it immediately initiates a new data transfer following the current one. repeated starts are commonly used during read operations to identify a specific memory address to begin a data transfer. a repeated start condition is issued identically to a normal start condition. see figure 1 for applicable timing. bit write: transitions of sda must occur during the low state of scl. the data on sda must remain valid and unchanged during the entire high pulse of scl plus the setup and hold time requirements (see figure 1 ). data is shifted into the device during the rising edge of the scl. bit read: at the end a write operation, the master must release the sda bus line for the proper amount of setup time (see figure 1 ) before the next rising edge of scl during a bit read. the device shifts out each bit of data on sda at the falling edge of the previous scl pulse and the data bit is valid at the rising edge of the current scl pulse. remember that the master generates all scl clock pulses including when it is reading bits from the slave. acknowledge (ack and nack): an acknowledge (ack) or not acknowledge (nack) is always the 9th bit transmitted during a byte transfer. the device receiving data (the master during a read or the slave during a write operation) performs an ack by transmitting a zero during the 9th bit. a device performs a nack by transmitting a one during the 9th bit. timing for the ack and nack is identical to all other bit writes. an ack is the acknowledgment that the device is properly receiving data. a nack is used to terminate a read sequence or as an indication that the device is not receiving data. byte write: a byte write consists of 8 bits of information transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgment from the slave to the master. the 8 bits transmitted by the master are done according to the bit write definition and the acknowledgment is read using the bit read definition. byte read: a byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ack or nack from the master to the slave. the 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition, and the master transmits an ack using the bit write definition to receive additional data bytes. the master must nack the last byte read to terminate communication so the slave returns control of sda to the master. figure 4. slave address byte 11 1 0r /w 0 0 0 msb lsb read/ write bit device identifier
16 DS1339A low-current, i 2 c, serial real-time clock slave address byte: each slave on the i 2 c bus responds to a slave address byte sent immediately following a start condition. the slave address byte contains the slave address in the most significant 7 bits and the r/ w bit in the least significant bit. the whatevers slave address is d0h and cannot be modified by the user. when the r/ w bit is 0 (such as in d0h), the master is indicating it writes data to the slave. if r/ w = 1, (d1h in this case), the master is indicating it wants to read from the slave. if an incorrect slave address is written, the DS1339A assumes the master is communicating with another i 2 c device and ignores the communication until the next start condition is sent. memory address: during an i 2 c write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. the memory address is always the second byte transmitted during a write operation following the slave address byte. i 2 c communication writing a single byte to a slave: the master must generate a start condition, write the slave address byte (r/ w = 0), write the memory address, write the byte of data, and generate a stop condition. remember the master must read the slaves acknowledgment during all byte write operations. writing multiple bytes to a slave: to write multiple bytes to a slave, the master generates a start condition, writes the slave address byte (r/ w = 0), writes the starting memory address, writes multiple data bytes, and generates a stop condition. reading a single byte from a slave: unlike the write operation that uses the specified memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address counter. to read a single byte from the slave, the master generates a start condition, writes the slave address byte with r/ w = 1, reads the data byte with a nack to indicate the end of the transfer, and generates a stop condition. however, since requiring the master to keep track of the memory address counter is impractical, the following method should be used to perform reads from a specified memory location. manipulating the address counter for reads: a dummy write cycle can be used to force the address counter to a particular value. to do this the master figure 5. i 2 c transactions sla ve address st ar t st ar t 1 1 0 1 0 0 0 sla ve ack slav e ack slav e ack r/w msb lsb msb lsb msb lsb b7 b6 b5 b4 b3 b2 b1 b0 read/ write register address b7 b6 b5 b4 b3 b2 b1 b0 da ta stop single byte write -write control register to b8h mul tibyte write -write da te register to "02" and month register to "11" single byte read -read control register mul tibyte read -read hours and da y register va lues st ar t repea ted st ar t d1h master nack stop 1 1010000 00001110 0eh 1 1010001 1101000 0 0 000111 0 d0h 0eh stop va lue st ar t 11010000 00000100 d0h 04h da ta master nack stop va lue da ta 02h b8h example i 2 c transactions typical i 2 c write transaction 10111000 00000010 d0h a) c) b) d) sla ve ack sla ve ack slav e ack sla ve ack sla ve ack sla ve ack slav e ack repea ted st ar t d1h master ack 1 1010001 va lue da ta slav e ack sla ve ack slav e ack st ar t 11010000 00000010 d0h 02h sla ve ack sla ve ack stop 11h 0001000 1 slav e ack
17 DS1339A low-current, i 2 c, serial real-time clock generates a start condition, writes the slave address byte (r/ w = 0), writes the memory address where it desires to read, generates a repeated start condition, writes the slave address byte (r/ w = 1), reads data with ack or nack as applicable, and generates a stop condition. see figure 5 for a read example using the repeated start condition to specify the starting memory location. reading multiple bytes from a slave: the read operation can be used to read multiple bytes with a single transfer. when reading bytes from the slave, the master simply acks the data byte if it desires to read another byte before terminating the transaction. after the master reads the last byte it must nack to indicate the end of the transfer and then it generates a stop condition. applications information power-supply decoupling to achieve the best results when using the DS1339A, decouple the v cc power supply with a 0.01 f f and/or 0.1 f f capacitor. use a high-quality, ceramic, surface- mount capacitor if possible. surface-mount components minimize lead inductance, which improves performance, and ceramic capacitors tend to have adequate high- frequency response for decoupling applications. using an open-drain output the sqw/ int output is open-drain and therefore requires an external pullup resistor to realize a logic-high output level. sda and scl pullup resistors sda is an open-drain output and requires an external pullup resistor to realize a logic-high output level. because the DS1339A does not use clock cycle stretching, a master using either an open-drain output with a pullup resistor or cmos output driver (push-pull) could be used for scl. battery charge protection the DS1339A contains maxims redundant battery- charge protection circuit to prevent any charging of an external battery. handling, pcb layout, and assembly avoid running signal traces under the package, unless a ground plane is placed between the package and the signal line. do not use external components to compen - sate for improper crystal selection. moisture-sensitive packages are shipped from the fac - tory dry-packed. handling instructions listed on the pack - age label must be followed to prevent damage during reflow. refer to the ipc/jedec j-std-020 standard for moisture-sensitive device (msd) classifications. figure 6. typical pcb layout for crystal crystal x1 x2 local ground plane (layer 2)
18 DS1339A low-current, i 2 c, serial real-time clock chip information process: cmos substrate connected to ground ordering information + denotes a lead(pb)-free/rohs-compliant package. package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. part temp range pin-package DS1339Au+ -40 n c to +85 n c 8 f sop package type package code outline no. land pattern no. 8-pin f sop u8+1 21-0036 90-0092
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated products, inc. 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 19 ? 2012 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 7/12 initial release DS1339A low-current, i 2 c, serial real-time clock

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